1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to testing of integrated memory within an integrated circuit.
2. Description of the Relevant Art
Integrated circuits have become ubiquitous in modern society. Products as diverse as automobiles, computer systems, televisions and telephones incorporate one or more integrated circuits to perform various functions. Generally speaking, an integrated circuit comprises circuitry formed upon a single monolithic semiconductor substrate. The integrated circuit implements one or more cores which perform the various functions of the integrated circuit as well as circuitry for communicating with other integrated circuits and devices external to the integrated circuit. A core is circuitry connected together to provide a desired high level function. For example, a processor core is circuitry which executes a set of instructions. Other cores may be a digital signal processing core configured to process signals, a cache controller core for managing a block of external memory as a cache, etc.
One popular type of integrated circuit is a microcontroller, which comprises a processor core as well as communications cores for various serial and parallel port connections to peripheral devices. Microcontrollers allow programmable control (via the processor core) of the peripherals connected thereto. Microcontrollers are commonly employed in a wide variety of devices including printers, cellular phones, automobiles, etc. Generally, a microcontroller is employed as the primary control chip in an electronic circuit embedded within a product other than a general purpose computer system (i.e. the so-called "embedded applications"). The microcontroller and related circuitry is employed to satisfy the computing demands of a product whose general purpose is not computing (i.e. a television, telephone, or automobile).
Modern microcontrollers incorporate not only a processor core and communications cores, but also integrate other devices commonly employed therewith. Particularly, microcontrollers have begun to integrate blocks of memory. Integrating previously discrete components such as memory may lead to cost savings in the final product, since fewer components are needed. However, integrating memory into a microcontroller generates the need to test the memory for functionality when the microcontroller is manufactured. Memories are generally constructed using minimum transistor dimensions, minimum spacing between transistors, and minimum-sized contacts. Therefore, memories are particularly vulnerable to defects introduced in the fabrication process. Defects can be introduced due to dust particles on the chips or the masks, scratches, gate oxide pinholes, and misalignment of masks, for example.
Typically, built in self-test (BIST) logic is included for performing the memory testing. The BIST logic is enabled when the test is desired, and the BIST logic reports the success or failure of the test in a manner which may be detected external to the microcontroller. For example, a pin may be asserted or deasserted. Alternatively, a status register may be updated, and the status register may be read to determine the pass/fail status of the BIST.
Memory defects may be classified as stuck-at faults, stuck-open faults, transition faults, state coupled faults, multiple access faults and data retention faults. A memory cell (or bit location) is said to be stuck-at if a read from the cell is always at a certain logic value regardless of the read/write activity performed on the cell or any influence from other cells. A memory cell is said to be stuck-open if it can never be accessed. A memory cell with a transition fault will fail to undergo at least one of the transitions from 0 to 1 or 1 to 0 when the cell is repeatedly written. A memory cell is said to be state coupled to another cell if the first cell is fixed at a certain value only if the second cell is in one defined state. The testing of state coupled faults requires demonstrating that any arbitrary pair of cells in the memory is able to be in 0-0,0-1,1-0, and 1-1 states. A memory cell is said to have a multiple access fault if a single read/write action accesses multiple cells. Finally, a memory cell with a data retention fault is unable to retain the charge stored therein (representing a binary one or a binary zero) for a minimum required period.
A 9N or 13N test algorithm (where N is the number of addresses in the memory and 9 or 13 refers to the number of accesses to each memory cell within one pass of the test) is typically employed by BIST logic to test all of the faults outlined above. Generally, the algorithms involve reading and writing both a selected "background" pattern and the complement of the background pattern. Once the memory is initialized to the selected background pattern, each memory cell is read to verify the selected background pattern, written with the complement of the background pattern, and then read again to verify the selected background pattern. The background pattern comprises a set of binary ones and zeros selected to stress cells which are physically located near one another. For example, the background patterns may be selected to update a cell to a binary one while an adjacent cell or cells is updated to a binary zero (and vice-versa). Other background patterns are selected such that a particular cell is updated to a binary one (or zero) while adjacent cells remain constant at a certain value. Further details regarding the 9N and 13N test algorithms may be found in Rob Dekker, Frans Beenker, Loek Thussen, "A Realistic Fault Model & Test Algorithms for Static Random Access Memories," IEEE Log Number 9034766 (Jul. 10, 1989), which is hereby incorporated by reference.
Unfortunately, the BIST logic presents an onerous design burden for microcontrollers and other integrated circuits. Microcontrollers are generally sold for relatively low prices and in high volumes, so microcontroller designs are extraordinarily cost-conscious designs. The die size of the semiconductor substrate is minimized to enhance yield and number of product produced per semiconductor wafer. The BIST logic may consume a significant amount of the available die area. It is possible, for example, for approximately 3-5% or even more of the die area to be dedicated to the BIST logic.
Another problem presented by the BIST logic is that it requires access to the memory. Therefore, the BIST logic's address, data, read/write controls, and other control signals must be incorporated into the ports (or access points) of the memory array. Multiplexors or other selection devices used to select between competing access requests must therefore include another input for the BIST logic. These multiplexors therefore become not only larger, but also slower, requiring additional time to propagate a value. Therefore, the clock cycle time (or frequency) achievable by the microcontroller may be impacted by the inclusion of the BIST logic. It is therefore desirable to provide an alternative to the BIST logic method of testing an integrated circuit having an integrated memory.